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Open Core Protocol Partners Off to Fast Start

By P J Connolly

February 1, 2008 — While some folks were recovering from their holidays, one consortium hit the ground running.

The Open Core Protocol International Partnership (OCP-IP) got the New Year off to a rousing start, adding six members and noting the beginning of the review of a new debug specification.

The new members, announced on Jan. 7, are Comtech EF Data, a manufacturer of satellite communications equipment; Cr?Vinn Teoranta, an ASIC and core design shop; ENSTA (?cole nationale sup?rieure de techniques avanc?es), France’s National Higher School of Advanced Techniques; Princeton University; Silicon Image, also in the business of core design; and Tata Elxsi, the technology arm of India’s Tata Group.

The next day, OCP-IP revealed that members had begun reviewing a new debug specification that supports a uniform method of accessing and analyzing on-chip systems and embedded information at the core, multicore and system level. It implements a debug interface socket that can be added to cores and blocks of intellectual property.

The goal of the specification is to address the increasingly diverse needs for prototyping hardware, software and mixed systems-on-chip, and intended to be compatible with other industry standards efforts, the group noted in its announcement.

The debug specification is a loose definition of requirements, and a set of debug signals that operate at the OCP socket and fabric levels, according to the group, which leaves specific implementation options to core designers and tool vendors.

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